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SPx: What is taking so long?

SPx: What is taking so long?

Some time ago, we have decided to break with the past, and raise the quality of our products to higher standards. This came at a time when ScanaPlus-x (the successor of ScanaPLUS) was almost ready for production. In this blog post, I'll be explaining some of the technical details that made us reconsider the launch of the product.

Input stage

Some may think that the input stage of a logic analyzer is a simple circuit with some logic buffers IC. While this may work in an idealistic world with low frequency signals that are perfectly square shaped, it won't work as well with "real world" signals, that have a certain amount of noise and relatively low rise and fall times.

As a matter of fact, a good input stage of a "digital" logic analyzer is very much an "analog" circuit, with amplification stages, level shifting hysteresis control, and analog bandwidth limits that need to be thoroughly studied.

As a side note, developing IkaScope oscilloscope gave us a huge experience in analog signal conditioning circuits, and we decided to re-build ScanaPlus-x input stage upon that know-how that we gained.

At the moment I'm writing those words, my team is currently testing and characterizing an input stage having those features:

  • 100KΩ // 4pF target impedance (to disturb measured signal as little as possible)
  • Large functional input range of -15V to +15V. By functional range, we mean that the signal is not clipped within that range, and the device can differentiate between a -5V and a -7V voltage level for example.
  • Adjustable logic thresholds withing the range of -7V to +7V
  • Adjustable hysteresis 
  • Threshold and hysteresis can be different for every channel
  • Analog Bandwidth well beyond 50MHz

You may notice we have put a great deal of effort into building an adjustable hysteresis system for each and every input channel. There's a reason for that. Hysteresis is one of the things that highly affects the quality of a captured signal. An input system with non-existing hysteresis will have glitches around signal transitions. Not very well configured hysteresis will affect the timing precision of captured signals (a perfectly square clock signal may look like a rectangular signal). Only a finely tuned hysteresis circuit will allow a signal to be captured with utmost fidelity.

Differential inputs

We really wanted to build the perfect input stage that can be configured to match differential signaling like CAN or RS485. While most CAN signals can be "tricked" into being captured with standard logic inputs, a real CAN-compliant input stage must take into account variation of common mode voltage of the CAN bus. For instance, most CAN buses will operate at a common mode voltage of 2.5V, but there is no guarantee whatsoever that this will always be true. Even during a single CAN frame, the common mode voltage may dramatically swing. Our better understanding of differential signals and our experience over the past few years led us to reconsider the differential input stage of ScanaPlus-x, even if it meant delaying the launch date of the product.


We have designed our own probes for SPx (ScanaPlus-x). That's right. We didn't just buy and package some of-the-shelf probes. We had a factory build the perfect probes according to our design and specifications. Our understanding of the market, and the usage of logic analyzers led us to believe that probes is one of the user's pain points. The probes are designed to give you a frustration free experience. We really hope you'll like them!


Here is a picture of the latest version of the probes, lying on my desk:

Logic analyzer custom probes

USB-2, compression, memory and Streaming

Here's an interesting set of information:

  • USB-2 can practically transfer 20 MB/s, not much more.
  • Signal Compression lets you overcome this bandwidth limit, by only sending an information when signal state is changing
  • Signal compression will eventually fail if it has to deal with a high frequency toggling signal for a long period of time: At some point, buffers will fill up and USB throughput won't be high enough to empty them. 
  • Embedded memory on a USB logic analyzer is limited and finite.

Given that information, we decided to build a system that makes the best of two worlds: Streaming and compression.

SPx will compress signals and stream them to the host computer. If at some point in time, captured signal toggling frequency is too high for USB streaming throughput, an internal memory kicks in to allow for up to 16 000 unique transitions to be stored and transferred when USB throughput allows it. If despite all those efforts, memory fills up too quickly, SPx will stop capturing signals, and gracefully end the capture. It will also let the user know exactly where in the signals did the capture stop prematurely.

While this compression and streaming algorithm was actually developed and tested a while ago, we decided to push the performance further by adding a bigger FPGA with more embedded memory.


Mar 05, 2018 • Posted by Ibrahim KAMAL

Hello Stefan,

Thank you for your message.

We can give an exact date now. All i can say is a prototype is being tested, and we should start production in a matter of 1~2 months.

We will send a mail when we have a confirmed launch date.

I am sorry that i can’t be more precise for now.

Feb 05, 2018 • Posted by Stefan

Hi IkaLogic team,

I like you are working on improving the ScanaPlus-x. For me the mentioned improvements definitely justify the postpone of the release. But can you give us at least rough estimation (e.g. possible quarters), when we can expect ScanPlus-x to be released?

Thank you,

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